package XunChunCPU

import chisel3._
import chisel3.util.Cat

class Test extends Module{
    val io = IO(new Bundle {
        val in = Input(UInt(16.W))
        val zero = Output(UInt(32.W))
        val sign = Output(UInt(32.W))
    })
    io.zero := Cat(0.U(16.W),io.in)
    when(io.in(15) === 1.U) {
        io.sign := Cat(0xffff.U(16.W),io.in)
    }.otherwise{
        io.sign := Cat(0.U(16.W),io.in)
    }
}